Soft Error Impact on FinFET and CMOS XOR Logic Gates

  • Rafael N. M. Oliveira Universidade Federal de Santa Catarina - UFSC
  • Cristina Meinhardt Universidade Federal de Santa Catarina - UFSC
Keywords: XOR topologies, PTL, CMOS logic family, XOR, FinFET, SET, radiation effects

Abstract

With the advance of computer systems, XORgates design became essential on arithmetic circuits.Atnanometer nodes, despite the electrical characterization, de-signers must to consider soft error impact on the circuits. Thechallenges change significantly as feature size are smaller, evenfor FinFET devices. The effects of Single Event Transientare dependent of the circuit topology. Thus, in this work, weevaluate the influence of nine XOR topologies on the radia-tion robustness, discussing the influence of logic family, the de-vice technology and environment factors as temperature, onthe radiation robustness. Also, this work explore the nominaland near-threshold operation of these XOR topologies. Resultsshows that FinFET devices are significantly more robust to theradiation effects. Also, most of PTL logic XORs topologiespresent about 40% of increase on the LET threshold. The de-pendence of temperature aggressively impact the FinFET tech-nology devices operating at near-threshold. Finally, the com-plete set of information provided in this work support design-ers to choose the most appropriate XOR topology accordingthe specific design requirements.

Published
2020-08-23
Section
Selected Papers from 19th Microelectronics Students Forum