A Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability
Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor to enhance stability. The performance of the proposed 8T SRAM cell with a stacked transistor has been analyzed based on the power consumption and static noise margin (RSNM, HSNM, and WSNM). The power consumption in the case of FinFET based 8T cell is found to be 572 pW at 22 nm technology node, which is reduced by a factor nearly as compared to that of CMOS based 8T cell. Further, in the case of FinFET based novel 8T SRAM cell at 22 nm technology node, the power consumption is found to be reduced by a factor of as compared to that of FinFET based conventional 6T SRAM cell. WSNM, HSNM, and RSNM of the 8T SRAM cell designed with FinFET logic are observed as 240 mV, 370 mV, and 120 mV respectively at 0.9 V supply voltage. When comparing with conventional 6T FinFET Cell, the proposed Cell shows 20%, 5.11%, and 7% improvement in WSNM, HSNM, and RSNM, respectively. The sensitivity of SNM with temperature variation is also analyzed and reported. Further, the results obtained confirm the robustness of the proposed SRAM cells as compared to several recent works.
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