Analysis of Current Mirrors with Asymmetric Self-Cascode Association of SOI MOSFETs through SPICE Simulations

Keywords: SOI nMOSFET transistor, Asymmetric self-cascode, Composite transistor, Current Mirror, SPICE Simulation.

Abstract

In this paper the performance of different architectures of current mirrors implemented with single SOI transistors and self-cascode transistors, both symmetric and asymmetric is evaluated. A comparison of current mirrors figures of merit, looking for the advantages of the asymmetric composite structure in relation to a single SOI MOSFETs and the symmetric self-cascode transistor is performed. This analysis has been carried out through analytical simulations, using common-source, Cascode and Wilson current mirrors architectures. It is shown that asymmetric configuration can provide larger output resistance even in the common-source current mirror than other architectures with conventional single transistors.

Published
2020-07-31
Section
Special Section on SBMicro2020