Study of the UTBB BESOI Tunnel-FET working as a Dual-Technology Transistor
In this work, we further investigate the operation of the BESOI (Back-Enhanced Silicon-On Insulator) Dual-Technology FET, analyzing not only its behavior as a p-type Tunnel-FET when a negative back bias is applied to the struc-ture, but also as an nMOS when a positive back bias is ap-plied. The working principle is based on the generation of a channel of either holes or electrons by the back gate electric field, which can then be depleted through the front gate bias. TCAD device simulation was used for the proof of concept.
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