The Implications of Ferroelectric FET Device Models to the Design of Computing-in-Memory Architectures

Keywords: Ferroelectric field-effect transistors, FeFETs, computing-in-memory, processing-in-memory, CiM, PIM, emerging technologies, beyond CMOS

Abstract

Data transfer between a processor and memory frequently represents a bottleneck with respect to improving application-level performance. Computing-in-memory (CiM), where logic and arithmetic operations are performed in memory, could significantly reduce both energy consumption and computational overheads associated with data transfer. This work presents a revisited study of FeFET-CiM, a CiM architecture capable of performing Boolean ((N)AND, (N)OR, X(N)OR, INV) as well as arithmetic (ADD) operations between words in memory. In this study, we employ two types of FeFET-based memory cells in the CiM architecture. Namely, the 2T+1FeFET and the 1-FeFET memory cells. The use of these two types of memory cells in the FeFET-CiM architecture is enabled by two distinct models for FeFET devices. The FeFET-CiM architecture based on 2T+1FeFETs (1FeFETs) offers an average speedup of ∼2.5X (∼1.1X) and energy reduction of ∼1.7X (∼1.4X) when compared to a SRAM baseline across 12 benchmark programs. Despite smaller speedups and energy savings enabled by 1FeFET-CiM when compared to 2T+1FeFET-CiM, 1FeFET memory arrays may offer up to ∼5.3X density improvements when compared to conventional 6T-SRAM arrays. Furthermore, 1FeFET-CiM offers significant application-level improvements when compared to a counterpart STT-CiM architecture.

Published
2021-04-05
Section
Special Issue on Future Trends in Nanocomputing