A Temperature-Aware Analysis of SAR ADCs for Smart Vehicle Applications

  • Adriano V. Fonseca GeePs, UMR CNRS 8507, CentraleSupélec, Université Paris-Saclay, Gif-sur-Yvette, France
  • Pietro Maris Ferreira GeePs, UMR CNRS 8507, Department of Electronic Systems, CentraleSupélec, Université Paris-Saclay http://orcid.org/0000-0002-0038-9058
  • Ludwig Cron GeePs, UMR CNRS 8507, CentraleSupélec, Université Paris-Saclay, Gif-sur-Yvette, France
  • Fernando A. P. Barúqui Universidade Federal do Rio de Janeiro - COPPE - PEE - Rio de Janeiro, RJ 21941-972, Brazil
  • Carlos F. T. Soares Universidade Federal do Rio de Janeiro - COPPE - PEE - Rio de Janeiro, RJ 21941-972, Brazil
  • Philippe Benabes GeePs, UMR CNRS 8507, CentraleSupélec, Université Paris-Saclay, Gif-sur-Yvette, France
Keywords: temperature-aware, latched comparators, SAR ADC, reliability, smart vehicle

Abstract

The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. The automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 ◦C. This proposal overviews an analysis of latched-comparators performance, considering process variability and temperature variation of previous works. This analysis is then extended to the metastability and performance metrics of successive approximation register (SAR) analog-to-digital converter (ADC) topology. Building blocks necessary for the SAR ADC are designed using an XH018 technology. Post-layout simulation results are drawn to validate the proposed temperature-aware analysis. Besides the known advantages of the Double-Tail comparator, this work demonstrates that such a comparator has a serious drawback under harsh environments. This proposal also shows that, once calibrated and operated at a frequency of around 100 MHz, the SAR ADC performance can be maintained in a wide temperature range. Both SA- and DT-SAR ADC achieve an ENOB of 9.8 bits, which is reduced to 9.6 bits in high-temperature operation. The results also show that background calibration is not required for the SAR ADC operation at the 100 MHz frequency range.

Published
2018-08-24