Memory-aware Workload Balancing Technique based on Decision Trees for Parallel HEVC Video Coding

  • Iago Storch Federal University of Pelotas
  • Bruno Zatt
  • Luciano Agostini
  • Guilherme Correa
  • Daniel Palomino
Keywords: Parallel video coding, workload balance, speedup, machine learning, memory-aware video coding

Abstract

Video coding applications demand high computational effort to achieve high compression rates at a low perceptual quality expense. In order to reach acceptable encoding time for such applications, modern video coding standards have been em-ploying parallelism approaches to exploit multiprocessing plat-forms, such as the tiling tool from HEVC standard. When employing Tiles, each frame is divided into rectangular-shaped regions which can be encoded independently. However, alt-hough it is possible to distribute the data equally among the processing units when using Tiles, balancing the workload among processing units poses great challenges. Therefore, this paper proposes a workload balancing technique aiming to speed up the HEVC parallel encoding using Tiles. Different from other literature works, the proposed solution uses a novel approach employing static uniform tiling to avoid memory management difficulties that may emerge when dynamic tiling solutions are employed. The proposed technique relies on workload distribution history of previous frames to predict the workload distribution of the current frame. Then, the pro-posed technique balances the workload among Tiles by em-ploying a workload reduction scheme based on decision trees in the coding process. Experimental tests show that the pro-posed solution outperforms the standard uniform tiling and it is competitive with related works in terms of speedup. Moreo-ver, the solution optimizes resources usage in multiprocessing platforms, presents a negligible coding efficiency loss and avoids increasing memory bandwidth usage by 9.8%, on aver-age, when compared to dynamic tiling solutions, which can impact significantly the performance in memory-constrained platforms.

Published
2020-12-28
Section
Selected Papers from 34º Simpósio Sul de Microeletrônica